As it is well known, semiconductor non-volatile memories, such as EPROM, EEPROM and flash memories, require, for the correct operation thereof, voltage values which are higher than a supply voltage reference VDD, and lower than a ground voltage reference GND.
In particular, the erasing operation of a non-volatile memory requires a positive overvoltage equal to about 10 volts (V) as well as a negative overvoltage equal to −8V, both generated from a supply voltage reference ranging between 1.8V and 5V and a ground voltage reference GND, that is conventionally equal to 0V.
To generate these positive and negative overvoltages, charge pump circuits are presently used. These circuits are generally realized by cascading a plurality of basic stages.
The most common charge pump circuit is the four-phase charge pump circuit, comprising a cascade of N driven basic stages, each one being driven by the two phases of a clock signal CK and \CK. For the correct operation of such a circuit, two consecutive basic stages must be driven by different phases and, thus, four phases are required to drive the whole charge pump circuit.
A basic stage for a known charge pump circuit is schematically shown in FIG. 1, globally indicated with 1.
The basic stage 1 has an input terminal IN connected to the input terminal of the charge pump circuit, if it is the first stage, or to an output terminal of a previous stage, as well as an output terminal connected to an input terminal of a following stage or to the output terminal of the charge pump circuit, if it is the last stage.
The basic stage 1 comprises first M1 and second M2 MOS transistors of the N-channel type having the conduction terminals connected to said input terminal IN and to first C1 and second C2 capacitors in correspondence with an internal circuit node X and of the output terminal OUT respectively. The transistors M1 and M2 also have the control terminals cross-connected to the output terminal OUT and to the internal circuit node X respectively.
The basic stage 1 also has first CK and second \CK driving signals applied to the capacitors C1 and C2; these driving signals being one opposite to the other.
It should be noted that only the second capacitor C2 is used for the charge transfer performed by the basic stage 1, the first capacitor C1 aiming only at generating a high overdrive voltage during the charging of the second capacitor C2.
The transistors M1 and M2 used in known charge pump circuits are usually of the “high-voltage” type since they must support a voltage being twice the circuit supply voltage VDD, applied to the control terminal thereof in particular operating conditions.
The cascade structure of a charge pump circuit using basic stages like the stage 1 is schematically shown in FIG. 2 and globally indicated with 2. The charge pump circuit 2 comprises a plurality of basic stages S1, S2, . . . , SN, each stage having the structure shown in FIG. 1.
It should be noted that the charge pump circuit 2 uses four driving signals A, \A, B and \B suitable to ensure a constant output power supply. In particular, they are step signals with different phases as shown in FIG. 3: it is, thus, possible to use frequencies that are too high since there is the risk of losing the right correlation required for the correct operation of the charge pump circuit 2.
The charge pump circuit 2 according to the prior art also requires a further output stage to reduce the ripple at the output terminal OUT of the last stage SN.
Also known is the use of a two-phase charge pump circuit, comprising a plurality of basic stages, both using the capacitors comprised in the structure to transfer the power at the output terminal.
Such a charge pump circuit is described, for example, in Italian patent application No. TO 2002A000158, filed on Feb. 25, 2002 which is filed in the name of the Applicant.
Particularly, the charge pump circuit according to this document comprises a plurality of basic stages as the one schematically shown in FIG. 4 and globally indicated with 3.
The basic stage 3 has a first node UP corresponding to the highest voltage node and a second node DOWN corresponding to the lowest voltage node.
Particularly, the node UP can be connected to the output terminal of a charge pump circuit comprising the basic stage 3 or to the input terminal (DOWN) of a following stage, while the node DOWN can be connected to a supply reference or to an output terminal (UP) of a previous stage.
The basic stage 3 comprises first MP1 and second MP2 MOS transistors of the P-channel type, having the conduction terminals connected to the node UP and to a first XL and second XR internal circuit nodes, respectively. The basic stage 3 also comprises third MN1 and fourth MN2 MOS transistors of the N-channel type, having the conduction terminals connected to the internal circuit nodes XL and XR, respectively, and to the node DOWN.
The first MP1 and third MN1 transistors realize a first inverter inserted between the nodes UP and DOWN and having the first internal circuit node XL as central point. Similarly, the second MP2 and the fourth MN2 transistors realize a second inverter inserted between the nodes UP and DOWN and having the second internal circuit node XR as central point.
The first transistor MP1 also has the control terminal connected to the control terminal of the third transistor MN1 as well as to the second internal circuit node XR. Similarly, the second transistor MP2 also has the control terminal connected to the control terminal of the fourth transistor MN2 as well as to the first internal circuit node XL.
The first and second transistors MP1 and MP2 also have the bulk terminals connected to the node UP, while the third MN1 and the fourth MN2 transistors have the bulk terminals connected to the node DOWN.
The basic stage 3 also comprises first CL and second CR capacitors connected to the nodes XL and XR, respectively, and receiving first CK and second CK_N driving signals.
It should be noted that the PMOS transistors MP1 and MP2 have the function of multiplexing the voltage values at the nodes XL and XR, connecting the highest voltage value node to the node UP.
The charge pump circuit obtained through a cascade of basic stages like the stage 3 requires only two driving signals and it is referred to as two-phase charge pump circuit. This allows higher frequencies to be used for these signals without risking the loss of synchronism of the basic stage cascade.
Moreover such a two-phase charge pump circuit has a voltage value which is substantially constant at the output terminal (corresponding to the node UP of the last cascade stage). The output voltage stability allows low-voltage transistors to be used, these transistors having lower size and greater conductivity characteristics with respect to the high-voltage transistors used in the four-phase charge pump circuits.
In substance, a two-phase charge pump circuit shows the following advantages: greater efficiency of the output power/input power ratio; possibility of using high frequency driving signals, thus decreasing the size of the capacitors to be used; and possibility of using low-voltage transistors, with a further decrease in the area occupied by the charge pump circuit.
Although advantageous in many aspects, this solution also shows several drawbacks. In particular, the charge pump circuit realized by means of the cascade of basic stages 3 has latch-up problems that can be caused by: forward biasing of the junctions P+/Nwell of the P-type MOS transistors; forward biasing of the junctions N+/Pwell of the N-channel MOS transistors. Suitable arrangements must, therefore, be provided in the layout phase of the charge pump circuit to avoid such a latch-up phenomenon.
Moreover, through the basic stage 3, it is impossible to realize a negative charge pump having only one stage, since the Nwell of the PMOS transistors cannot reach negative voltage values.